1. Field of the Invention
The present invention relates to a semiconductor substrate having a silicon-on-insulator (SOI) structure where a thinned crystalline semiconductor layer is provided on an insulating substrate. The present invention particularly relates to a bonding SOI technique and also relates to a semiconductor substrate which is obtained by providing a crystalline semiconductor layer for a substrate having an insulating surface using glass or the like. The present invention further relates to a semiconductor device using such a semiconductor substrate or a method for manufacturing the semiconductor device.
2. Description of the Related Art
Instead of a silicon wafer that is formed by thinly slicing an ingot of a single crystal semiconductor manufactured by a Czochralski (CZ) method or the like, a semiconductor substrate called a silicon-on-insulator substrate (SOI substrate) has been developed, in which a thin single crystal semiconductor layer is provided over a substrate having an insulating surface.
As a typical method for manufacturing an SOI substrate, a hydrogen ion implantation separation method is known (for example, see Reference 1: U.S. Pat. No. 6,372,609). A hydrogen ion implantation separation method is a method in which hydrogen ions are implanted into a silicon wafer, whereby a microbubble layer is formed in a region at a predetermined depth from a surface of the silicon wafer; the surface into which the hydrogen ions are implanted is superposed on another silicon wafer; and heat treatment is performed to separate the silicon wafer using the microbubble layer as a cleavage plane, so that a thin single crystal silicon layer (SOI layer) that is bonded to the another silicon layer is formed. In accordance with this method, in addition to heat treatment by which an SOI layer that is a surface layer is separated, heat treatment is required to be performed in the reducing atmosphere at 1000° C. to 1300° C. in order to increase the bonding strength.
Further, since parasitic capacitance of a transistor can be reduced with the use of the SOI substrate, formation of an integrated circuit using the transistor has been expected to be effective for improvement of operation speed and reduction in consumption power. For example, a fully-depletion field effect transistor that includes a ultrathin SOI layer is disclosed (see Reference 2: Japanese Published Patent Application No. H11-284201).